1. Field of the Invention
The present invention relates to a semiconductor testing apparatus, a semiconductor integrated-circuit device, and semiconductor integrated-circuit device testing method and fabricating method. More particularly, it relates to a technology that is effective when applied to the implementation of a high efficiency in the memory test for a synchronous DRAM or the like.
2. Description of the Related Art
In general, in a semiconductor integrated-circuit device, various types of tests are carried out before the shipment thereof or the like. One example is a function test for confirming whether or not the semiconductor memory operates exactly in accordance with a predetermined function as was expected. These tests make a selection between a good die and a defective one.
FIG. 13 is a configuration diagram of a tester 30 that the present inventor has devised and examined. The tester 30 tests the semiconductor integrated-circuit device, e.g. the synchronous DRAM.
The tester 30 includes a pattern generator 31, a comparator 32, interface circuits 33, and the like. The pattern generator 31 generates an application pattern to be applied to input pins of the semiconductor memory, i.e., device-under-test and an expectation pattern expected of output pins thereof, respectively.
The comparator 32 makes a comparison between a response pattern from the semiconductor memory and the expectation pattern thereof, thereby judging whether the semiconductor memory is passing or defective. The interface circuits 33 are interfaces located between the tester 30 and the semiconductor integrated-circuit device.
The tester 30 includes n units of the interface circuits 33. Each interface circuit 33 includes drivers 33a and comparators 33b, which are connected to the pins of the semiconductor integrated-circuit device.
If the tester 30 has the interface circuits that are equivalent to, e.g., 128 pins in number (i.e., 128 units), in the case of a semiconductor integrated-circuit device having 32 pins, it turns out that 4 units of the semiconductor integrated-circuit devices at the maximum are connected to the tester and are tested simultaneously.
The drivers 33a are connected to the input pins of the semiconductor integrated-circuit device, respectively. The application pattern is applied to the input pins of the semiconductor integrated-circuit device via these drivers 33a. The comparators 33b, based on voltage-level judgements, convert the output response, which is outputted from the semiconductor integrated-circuit device, into logical values (: H/L), then outputting the logical values to the comparator 32.
Also, FIG. 14 is a configuration diagram for illustrating an example of the test pattern used in the tester 30, and FIG. 15 is an operation timing chart therefor.
FIG. 14 illustrates, from the left to the right, the following information, respectively: Commands outputted from the tester 30 to the semiconductor integrated-circuit device, i.e., the device-under-test, signal states in the data pins of the semiconductor integrated-circuit device, states of the signals inputted/outputted into/from the semiconductor integrated-circuit device, and signal states inside the semiconductor integrated-circuit device.
FIG. 15 illustrates, from the above to the below, the following information, respectively: The commands outputted from the tester 30 to the semiconductor integrated-circuit device, the signal states in the data pins of the semiconductor integrated-circuit device, the signal states inside the semiconductor integrated-circuit device, and the states of the signals inputted/outputted into/from the semiconductor integrated-circuit device.
In this example, subsequently to a ‘Write’ command, 2 ‘Nop’ commands and a ‘Read’ command are given one after another. At this time, the data pins provide write data at an input mode into the semiconductor integrated-circuit device. Otherwise, at the time of a read operation, the data pins receive read data that is returned thereto at an output mode from the semiconductor integrated-circuit device.
Also, some of the semiconductor integrated-circuit devices integrate therein a testing circuit for testing the logical gates from a small number of external terminals and with a high efficiency.
As a configuration of this testing circuit, there exists, e.g., the BIST (: Built In Self Test). The BIST integrates therein tester functions such as a test-pattern generating circuit, a test-output compressing circuit, and a test-result judging circuit. Namely, the BIST is a circuit that makes it possible to carry out the self test without using an external tester.
As the test-pattern generating circuit, an apparatus such as the LFSR (: Linear Feedback Shift Register) is employed which generates a random number. The test-pattern generating circuit has allowed the running of the pseudo random test and that of the all-number test for testing all the patterns.
Moreover, the test-output compressing circuit also employs the LFSR therein. The use of the LFSR allows the output-response pattern sequence to be compressed. Then, a comparison is made between a value that remains last and a correct expectation value, thereby carrying out the test.
Incidentally, as an example that has given a detailed explanation concerning this type of tester, there exists JP-A-2000-97998. This literature has disclosed a semiconductor testing apparatus that is capable of testing a semiconductor device such as the system LSI in a short time.